1. Field of the Invention
The present invention relates to a high voltage integrated circuit device (HVIC). In particular, the invention relates to a high voltage integrated circuit device such that malfunction due to an overcurrent flowing when a negative voltage surge is input into a circuit is prevented from occurring.
2. Description of the Background Art
An element isolation type of HVIC that utilizes a high breakdown voltage junction is used in a method of driving a switching power device configuring the upper arm of a power conversion (direct current to alternating current conversion) bridge circuit such as a PWM inverter. The HVIC has increased functionality, including the functions of overcurrent detection and temperature detection when trouble occurs in the switching power device, and there is no carrying out of electrical isolation by a transformer, photocoupler, or the like, because of which it is possible to achieve a reduction in size and a reduction in cost of a power supply system.
FIG. 7 is an illustration showing an example of the connection of a switching power device of a power conversion device, such as an inverter, and an existing HVIC that drives the switching power device. FIG. 7 shows an example of a half-bridge wherein two switching power devices (herein, IGBTs 114 and 115) are connected in series. The power conversion device shown in FIG. 7 is such that a high potential and low potential are output alternately from a Vs terminal, which is an output terminal, by the upper arm IGBT 115 and lower arm IGBT 114 being turned on alternately, thereby supplying alternating current power (causing alternating current to flow) to an L load 118.
That is, when outputting a high potential, the IGBT 114 and IGBT 115 are caused to operate so that the upper arm IGBT 115 is turned on and the lower arm IGBT 114 is turned off. Also, conversely, when outputting a low potential, the IGBT 114 and IGBT 115 are caused to operate so that the upper arm IGBT 115 is turned off and the lower arm IGBT 114 is turned on. Diodes connected in anti-parallel to the IGBTs 114 and 115 are free wheeling diodes (FWD) 116 and 117. In this period, in an HVIC 111 that is a drive element, a gate signal to the lower arm IGBT 114 is such that the signal is output using a GND reference, and a gate signal to the upper arm IGBT 115 is such that the signal is output using a Vs terminal reference. Therefore, it is necessary that the HVIC 111 includes a level shift function.
Of the reference signs in FIG. 7, Vss is the high potential side of a high voltage power supply, which is a main circuit power supply. GND is the ground. Vs is an intermediate potential that fluctuates between the Vss potential and GND potential. H-VDD is the high potential side of a second low voltage power supply 113 having Vs as a reference. L-VDD is the high potential side of a first low voltage power supply 112 having GND as a reference. When the second low voltage power supply 113 is a bootstrap circuit type, it is configured of an external capacitor (not shown) charged by an external bootstrap diode (not shown) connected between the L-VDD and H-VDD.
Also, H-IN is an input signal input into the gate of a low side C-MOS circuit connected to a level-up circuit, and an input terminal. L-IN is an input signal input into the gate of a low side C-MOS circuit connected to the gate of the lower arm IGBT 114, and an input terminal. Also, H-OUT is a high side C-MOS circuit output signal output to the gate of the upper arm IGBT 115, and an output terminal. L-OUT is an output signal output to the gate of the lower arm IGBT 114, and an output terminal. Also, ALM-IN is an input signal of a detection signal 119 when the temperature or an overcurrent of the upper arm IGBT 115 is detected, and an input terminal. ALM-OUT is an output signal of a detection signal of which the level has been lowered, and an output terminal.
FIGS. 8 and 9 are circuit diagrams showing level shifter circuits inside the HVIC 111 shown in FIG. 7, and circuits peripheral to the level shifter circuits. FIG. 8 is a circuit diagram including a level-up circuit, while FIG. 9 is a circuit diagram including a level-down circuit. In FIGS. 8 and 9, reference number 120 is a high potential side terminal of the second low voltage power supply 113 shown in FIG. 7, which has the intermediate potential Vs as a reference.
Herein, a low side C-MOS circuit that transmits input signals of the level shifter circuit, and a high side C-MOS circuit that transmits output signals of the level shifter circuit to the upper arm IGBT 115, are shown as the peripheral circuits. In the following description, p indicates p-type and n indicates n-type.
In FIG. 8, on an input signal (H-IN) being input into the low side circuit, the signal is input via the C-MOS circuit of the low side circuit into the gate of an n-channel MOSFET 41 of the level-up circuit. The n-channel MOSFET 41 is turned on or off by this signal, an output signal of the level-up circuit is output from an output portion 101, the C-MOS circuit of the high side circuit is turned on or off in accordance with the signal, and an output signal (H-OUT) is output. The output signal is converted into a signal having the intermediate potential Vs as a reference. The output signal is input into the gate of the upper arm IGBT 115, thereby causing the upper arm IGBT 115 to be turned on or off. The level-up circuit of FIG. 8 is necessary when the upper arm IGBT 115 is an n-channel type.
In FIG. 9, the level-down circuit is configured of a p-channel MOSFET 43 and a level shift resistor 72. A diode 76 is connected in parallel with the level shift resistor 72. The ALM-IN signal is input into the gate of the C-MOS circuit of the high side circuit, and an output signal of the C-MOS circuit is input into the gate of the p-channel MOSFET 43 of the level-down circuit. By the p-channel MOSFET 43 being turned on or off, a low side signal is output from an output portion 102 of the level-down circuit, and a signal of which the level has been lowered from the output of the C-MOS circuit of the low side circuit is output as a detection signal from ALM-OUT to the low side.
As well as in motor control inverters, switching power devices are widely utilized in a large number of fields, such as power supply applications for large capacity plasma display panels (PDP), liquid crystal panels, and the like, and inverters for household electrical appliances such as air conditioners and lighting, and as well as IGBTs, power MOSFETs are also used.
Motors, lighting, and the like, form the kind of inductance load shown in FIG. 7. Therefore, the Vs terminal and H-VDD terminal of the HVIC are affected by parasitic inductance, or the like, caused by wiring on a printed substrate, cable to the load, or the like. Due to the parasitic inductance, the Vs terminal and H-VDD terminal of the HVIC 111 fluctuate to the negative potential side with respect to the ground (the GND terminal of FIG. 7) when the upper arm IGBT 115 is turned off. This fluctuation causes element destruction due to malfunction or latch-up of the high side circuit.
FIGS. 10A and 10B are detailed diagrams of the level shifter circuit of the existing HVIC. FIG. 10A is a level-up circuit diagram, and FIG. 10B is a level-down circuit diagram.
The level-up circuit shown in FIG. 10A is configured to include a level shift resistor 71 and the n-channel MOSFET 41, of which the drain is connected to the level shift resistor 71, wherein a connection portion of the level shift resistor 71 and n-channel MOSFET 41 is adopted as the output portion 101 of the level-up circuit.
When the H-VDD is of a potential considerably lower than the GND potential (when an excessive negative voltage surge is applied) as heretofore described, a diode 75 is connected in parallel with the level shift resistor 71 in order to prevent thermal destruction of the level shift resistor 71. Also, when an overvoltage is applied to the H-VDD, the diode 75 has a function of preventing an excessive voltage from being applied to the gate of the MOSFET of the high side circuit C-MOS circuit. Normally, a Zener diode is used as the diode 75. Also, a body diode 42 is incorporated in anti-parallel with the n-channel MOSFET 41.
Meanwhile, the level-down circuit shown in FIG. 10B is configured to include the drain of the p-channel MOSFET 43 and the level shift resistor 72 connected to the drain, wherein a connection portion of the level shift resistor 72 and p-channel MOSFET 43 is adopted as the output portion 102 of the level-down circuit.
When the H-VDD is of a potential considerably lower than the GND potential, the diode 76 is connected in parallel with the level shift resistor 72 in order to prevent thermal destruction of the level shift resistor 72. Also, when an overvoltage is applied to the H-VDD when the p-channel MOSFET 43 carries out a turn-on operation, the diode 76 has a function of preventing an overvoltage from being applied to the gate of the MOSFET of the low side circuit C-MOS circuit. Also, the diode 76 has a function of preventing an overvoltage from being applied to the H-VDD when the p-channel MOSFET 43 carries out a turn-on operation. Also, a body diode 44 is connected in anti-parallel with the p-channel MOSFET 43.
FIG. 11 is sectional views showing logic portions of a high side circuit and low side circuit of an existing self-isolation type of high voltage integrated circuit device 500, and main portions of a level-up circuit portion and high voltage junction terminal region (HVJT). Reference sign 21 in FIG. 11 is a p-type offset region. Reference signs 22 to 24, 26 to 28, 32 to 34, and 36 to 38 in FIG. 11 are regions that form sources, drains, and contacts. Also, reference signs 25, 29, 35, and 39 are gate electrodes. Although not shown, a gate oxide film is formed between each gate electrode and a substrate 1. Also, although not shown, an interlayer dielectric and protective film are formed on the gate oxide film.
In FIG. 11, an n-type well region 2 and an n-type well region 3 are formed in a surface layer of the p-type substrate 1, which is connected to a GND potential. For example, a C-MOS circuit, or the like, of the low side circuit is formed inside the n-type well region 2. For example, a C-MOS circuit, or the like, of a level shifter circuit or the high side circuit is formed inside the n-type well region 3.
The level shifter n-channel MOSFET 41 includes an n−-type well region 4 that forms a voltage resistant region, a p-type well region 51 in contact with the n−-type well region 4, an n-type source region 53 and p-type contact region 56 formed in a surface layer of the p-type well region 51, an n-type drain region 52 formed in a surface layer of the n−-type well region 4, and a gate electrode 55 formed across a gate oxide film (not shown) on the p-type well region 51 sandwiched by the n-type source region 53 and n-type drain region 52.
The n-type drain region 52 of the n-channel MOSFET 41 is connected by surface metal wiring to the H-VDD via the level shift resistor 71. The high voltage integrated circuit device 500 is such that a connection portion of the n-type drain region 52 of the n-channel MOSFET 41 and the level shift resistor 71 is adopted as the output portion 101 of the level-up circuit.
The output portion 101 outputs a low potential when the level-up n-channel MOSFET 41 is turned on, and outputs a high potential when the n-channel MOSFET 41 is turned off. Therefore, the high voltage integrated circuit device 500 can carry out a level shift operation, which is a signal transmission between differing reference potentials.
As heretofore described, a surge of negative potential with respect to the GND potential enters the Vs terminal at the timing at which the upper arm IGBT 115 is turned off. This intermediate voltage Vs can be calculated using the following Expression 1.Vs=L×dI/dt  (1)
When the intermediate voltage Vs becomes lower than a value which is the value of Vsupply and Vf added together subtracted from the GND potential, an internal parasitic diode of the semiconductor chip begins to conduct. Vsupply is the battery voltage across the second low voltage power supply 113 or an unshown bootstrap capacitor, and Vf is the forward voltage drop of parasitic diodes 45 and 46.
When the intermediate voltage Vs is pulled a long way in the negative direction, an overcurrent flows through the chip, as a result of which there is concern that the high side circuit will malfunction, and the chip be damaged. For the period for which there is negative voltage, a spike form negative surge is applied to the Vs terminal at in the region of, for example, −30V for a period of around several hundred nanoseconds to in the region of 500 nanoseconds, in proportion to the product of parasitic inductance (L1) caused by wiring on the printed substrate from the HVIC 111, cable to the load, and the like, and dI1/dt in an off-state period of an on-state current I1 caused to flow through the IGBT 115.
FIG. 12 is a deployment diagram showing main portions of the high side circuit, level shifter, and the like, of FIG. 11. An H-VDD pad, H-OUT pad, Vs pad and intermediate potential region are formed in the n-type well region 3, which is a high potential region. A Vs potential region 81, which is an intermediate potential region, is a p-type offset region 31 and the p-type drain region 34 of FIG. 11. A second high concentration region 62, which is an n-type contact region, is formed in band-form in a surface layer on the outer periphery of the n-type well region 3. A second pickup electrode 203 is disposed on the second high concentration region 62. The n−-type well region 4, which is a voltage resistant region, is formed enclosing the n-type well region 3. A p-type common potential region 61 is formed enclosing the n−-type well region 4. An H-VDD potential region 82 is a region in which are formed the n-type contact region 32, p-type source region 33, and the like, shown in FIG. 11.
Also, a first high concentration region 56, which is a p-type contact region, is formed in band-form in a surface layer of the p-type common potential region 61. A first pickup electrode 202 is disposed on the first high concentration region 56. Herein, for the sake of convenience, the first and second pickup electrodes 202 and 203 are shown as dotted black squares.
The dotted black squares represent metals that fill unshown contact holes, formed in an interlayer dielectric and a protective film, that link the pickup electrodes 202 and 203 and the first and second high concentration regions 56 and 62.
An n-type well region 2, which is a low potential region, is formed in contact with the p-type common potential region 61 and enclosing the p-type common potential region 61. The GND reference low side circuit shown in FIG. 11 is formed in the n-type well region 2. The p-type well region 51 is formed in a surface layer of the p-type substrate 1 sandwiched between the n-type well region 2 and n−-type well region 4. The n-channel MOSFET 41 of the level shifter is formed in a surface layer of the p-type well region 51. Also, a high voltage junction terminal region (HVJT) is configured of the second high concentration region 62 and p-type common potential region 61 and the n−-type well region 4 sandwiched between these regions. The p-type well region 51 and n−-type well region 4 in which the level shifter is formed are in contact.
When attempting to reduce the chip size by disposing each of the previously described regions efficiently and without waste, one portion of the Vs potential region 81, which is an intermediate potential region, is disposed adjacent to the second high concentration region 62. When taking the place of the adjacent portion to be reference sign E (refer to FIG. 12), place E is a place in which the Vs potential region 81, which is an intermediate potential region, and the second high concentration region 62 of the high voltage junction terminal region (HVJT) oppose each other. Therefore, place E is the place where the distance at which the Vs potential region 81, which is an intermediate potential region, and the high voltage junction terminal region (HVJT) oppose each other is smallest (hereafter referred to as the opposing place E).
As this kind of high voltage integrated circuit, a more detailed description of a high voltage integrated circuit chip is given in JP-A-2001-210972 to International Publication 2012-176347.
A circuit for protecting a high voltage integrated circuit that drives a power transistor with a half-bridge configuration is shown in JP-A-2001-210972. The circuit being a circuit that allows for an excessive negative swing at an output node (point), a high voltage integrated circuit chip having a resistor that limits current during a negative voltage spike between the substrate and the ground is disclosed.
Also, a device such that the effect of reverse bias is reduced by a diode being inserted between the drain electrode of a switching element belonging to a level shifter and the gate electrode of a MOS transistor belonging to an amplifier (C-MOS circuit) is disclosed as a high voltage integrated circuit device in JP-A-2001-25235.
Also, as another high voltage integrated circuit device, it is disclosed in JP-A-2008-301160 that the drain of a switching element belonging to a level shifter, a level shift resistor, and a current limiting resistor are connected in series, and a portion between the level shift resistor and current limiting resistor is adopted as an output portion of a level-up circuit.
Also, the following device is disclosed as another high voltage integrated circuit device in JP-A-2010-263116. A high breakdown voltage diode (D3) is provided between a common ground node (COM) and a virtual ground node (Vs) inside a high voltage integrated circuit (HVIC) by utilizing a common substrate region. It is disclosed that, by so doing, a drop in high potential side power supply voltage due to negative voltage undershoot occurring in the high potential side reference potential (virtual ground Vs) is reliably suppressed in a power device drive circuit.
Also, a description is given of a power device drive circuit as another high voltage integrated circuit device in International Publication 2012-176347. In this power device drive circuit, the contact of a high voltage junction terminal region portion in a place physically near a high potential side reference potential (virtual ground Vs) is reduced, or the length of a voltage resistant region is increased, and a double RESURF structure is partially added. It is disclosed that, by so doing, there is a reduction in the amount of carriers implanted into the high potential side reference potential (virtual ground Vs) in accompaniment to a drop in the high potential side power supply voltage caused by negative voltage undershoot.